include/asm-i386/smp.h

12249 #ifndef __ASM_SMP_H
12250 #define __ASM_SMP_H
12251 
12252 /* We need the APIC definitions automatically as part of
12253  * 'smp.h' */
12254 #include <linux/config.h>
12255 #ifdef CONFIG_X86_LOCAL_APIC
12256 #ifndef ASSEMBLY
12257 #include <asm/fixmap.h>
12258 #include <asm/i82489.h>
12259 #include <asm/bitops.h>
12260 #endif
12261 #endif
12262 
12263 #ifdef __SMP__
12264 #ifndef ASSEMBLY
12265 
12266 #include <linux/tasks.h>
12267 #include <linux/ptrace.h>
12268 
12269 /* Support definitions for SMP machines following
12270  * the intel multiprocessing specification */
12271 
12272 /* This tag identifies where the SMP configuration
12273  * information is.  */
12274 
12275 #define SMP_MAGIC_IDENT                                 \
12276   (('_'<<24)|('P'<<16)|('M'<<8)|'_')
12277 
12278 struct intel_mp_floating
12279 {
12280   char mpf_signature[4];      /* "_MP_" */
12281   unsigned long mpf_physptr;  /* Config table address */
12282   unsigned char mpf_length;   /* Our len (paragraphs) */
12283   unsigned char mpf_specification;/* Spec version */
12284   unsigned char mpf_checksum; /* Checksum (makes sum 0)*/
12285   unsigned char mpf_feature1; /* Std or configuration? */
12286   unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
12287   unsigned char mpf_feature3; /* Unused (0) */
12288   unsigned char mpf_feature4; /* Unused (0) */
12289   unsigned char mpf_feature5; /* Unused (0) */
12290 };
12291 
12292 struct mp_config_table
12293 {
12294   char mpc_signature[4];
12295 #define MPC_SIGNATURE "PCMP"
12296   unsigned short mpc_length;      /* Size of table */
12297   char  mpc_spec;                 /* 0x01 */
12298   char  mpc_checksum;
12299   char  mpc_oem[8];
12300   char  mpc_productid[12];
12301   unsigned long mpc_oemptr;       /* 0 if not present */
12302   unsigned short mpc_oemsize;     /* 0 if not present */
12303   unsigned short mpc_oemcount;
12304   unsigned long mpc_lapic;        /* APIC address */
12305   unsigned long reserved;
12306 };
12307 
12308 /* Followed by entries */
12309 
12310 #define MP_PROCESSOR    0
12311 #define MP_BUS          1
12312 #define MP_IOAPIC       2
12313 #define MP_INTSRC       3
12314 #define MP_LINTSRC      4
12315 
12316 struct mpc_config_processor
12317 {
12318   unsigned char mpc_type;
12319   unsigned char mpc_apicid;       /* Local APIC number */
12320   unsigned char mpc_apicver;      /* Its versions */
12321   unsigned char mpc_cpuflag;
12322 #define CPU_ENABLED       1  /* Processor is available */
12323 #define CPU_BOOTPROCESSOR 2  /* Processor is the BP */
12324   unsigned long mpc_cpufeature;
12325 #define CPU_STEPPING_MASK 0x0F
12326 #define CPU_MODEL_MASK  0xF0
12327 #define CPU_FAMILY_MASK 0xF00
12328   unsigned long mpc_featureflag; /* CPUID feature value*/
12329   unsigned long mpc_reserved[2];
12330 };
12331 
12332 struct mpc_config_bus
12333 {
12334   unsigned char mpc_type;
12335   unsigned char mpc_busid;
12336   unsigned char mpc_bustype[6] __attribute((packed));
12337 };
12338 
12339 #define BUSTYPE_EISA    "EISA"
12340 #define BUSTYPE_ISA     "ISA"
12341 #define BUSTYPE_INTERN  "INTERN"  /* Internal BUS */
12342 #define BUSTYPE_MCA     "MCA"
12343 #define BUSTYPE_VL      "VL"      /* Local bus */
12344 #define BUSTYPE_PCI     "PCI"
12345 #define BUSTYPE_PCMCIA  "PCMCIA"
12346 
12347 /* We don't understand the others */
12348 
12349 struct mpc_config_ioapic
12350 {
12351   unsigned char mpc_type;
12352   unsigned char mpc_apicid;
12353   unsigned char mpc_apicver;
12354   unsigned char mpc_flags;
12355 #define MPC_APIC_USABLE         0x01
12356   unsigned long mpc_apicaddr;
12357 };
12358 
12359 struct mpc_config_intsrc
12360 {
12361   unsigned char mpc_type;
12362   unsigned char mpc_irqtype;
12363   unsigned short mpc_irqflag;
12364   unsigned char mpc_srcbus;
12365   unsigned char mpc_srcbusirq;
12366   unsigned char mpc_dstapic;
12367   unsigned char mpc_dstirq;
12368 };
12369 
12370 #define MP_INT_VECTORED         0
12371 #define MP_INT_NMI              1
12372 #define MP_INT_SMI              2
12373 #define MP_INT_EXTINT           3
12374 
12375 #define MP_IRQDIR_DEFAULT       0
12376 #define MP_IRQDIR_HIGH          1
12377 #define MP_IRQDIR_LOW           3
12378 
12379 
12380 struct mpc_config_intlocal
12381 {
12382   unsigned char mpc_type;
12383   unsigned char mpc_irqtype;
12384   unsigned short mpc_irqflag;
12385   unsigned char mpc_srcbusid;
12386   unsigned char mpc_srcbusirq;
12387   unsigned char mpc_destapic;
12388 #define MP_APIC_ALL     0xFF
12389   unsigned char mpc_destapiclint;
12390 };
12391 
12392 
12393 /*      Default configurations
12394  *
12395  *      1   2 CPU ISA 82489DX
12396  *      2   2 CPU EISA 82489DX no IRQ 8 or timer chaining
12397  *      3   2 CPU EISA 82489DX
12398  *      4   2 CPU MCA 82489DX
12399  *      5   2 CPU ISA+PCI
12400  *      6   2 CPU EISA+PCI
12401  *      7   2 CPU MCA+PCI */
12402 
12403 /* Private routines/data */
12404 
12405 extern int smp_found_config;
12406 extern void init_smp_config(void);
12407 extern unsigned long smp_alloc_memory(
12408   unsigned long mem_base);
12409 extern unsigned char boot_cpu_id;
12410 extern unsigned long cpu_present_map;
12411 extern unsigned long cpu_online_map;
12412 extern volatile int cpu_number_map[NR_CPUS];
12413 extern volatile unsigned long smp_invalidate_needed;
12414 extern void smp_flush_tlb(void);
12415 
12416 extern volatile unsigned long cpu_callin_map[NR_CPUS];
12417 extern void smp_message_irq(int cpl, void *dev_id,
12418                             struct pt_regs *regs);
12419 extern void smp_send_reschedule(int cpu);
12420 extern unsigned long ipi_count;
12421 extern void smp_invalidate_rcv(void); /* Process NMI */
12422 extern void smp_local_timer_interrupt(
12423   struct pt_regs * regs);
12424 extern void (*mtrr_hook) (void);
12425 extern void setup_APIC_clock (void);
12426 extern volatile int __cpu_logical_map[NR_CPUS];
12427 extern inline int cpu_logical_map(int cpu)
12428 {
12429   return __cpu_logical_map[cpu];
12430 }
12431 
12432 
12433 /* General fns that each host system must provide. */
12434 
12435 extern void smp_callin(void);
12436 extern void smp_boot_cpus(void);
12437 /* Store per CPU info (like the initial udelay numbers */
12438 extern void smp_store_cpu_info(int id);
12439 
12440 /* This function is needed by all SMP systems. It must
12441  * _always_ be valid from the initial startup. We map
12442  * APIC_BASE very early in page_setup(), so this is
12443  * correct in the x86 case.  */
12444 
12445 #define smp_processor_id() (current->processor)
12446 
12447 extern __inline int hard_smp_processor_id(void)
12448 {
12449   /* we don't want to mark this access volatile - bad
12450    * code generation */
12451   return GET_APIC_ID(*(unsigned long *)
12452                      (APIC_BASE+APIC_ID));
12453 }
12454 
12455 #endif /* !ASSEMBLY */
12456 
12457 #define NO_PROC_ID 0xFF /* No processor magic marker */
12458 
12459 /* This magic constant controls our willingness to
12460  * transfer a process across CPUs. Such a transfer incurs
12461  * misses on the L1 cache, and on a P6 or P5 with
12462  * multiple L2 caches L2 hits. My gut feeling is this
12463  * will vary by board in value. For a board with separate
12464  * L2 cache it probably depends also on the RSS, and for
12465  * a board with shared L2 cache it ought to decay fast as
12466  * other processes are run.  */
12467 
12468 #define PROC_CHANGE_PENALTY     15 /* Schedule penalty */
12469 
12470 #endif
12471 #endif